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Features
* * * * * * * * * * * * * * *
First-in First-out Dual Port Memory 4096-bit x 9 Organization Fast Flag and Access Times: 15, 30 ns Wide Temperature Range: -55C to +125C Fully Expandable by Word Width or Depth Asynchronous Read/Write Operations Empty, Full and Half Flags in Single Device Mode Retransmit Capability Bi-directional Applications Battery Backup Operation: 2V Data Retention TTL Compatible Single 5V 10% Power Supply No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2 Tested up to a Total Dose of 30 krads (Si) according to MIL STD 883 Method 1019 Quality grades : QML Q and V with SMD 5962-89568 and ESCCwith specification 9301/049
Rad. Tolerant High Speed 4 Kb x 9 Parallel FIFO M67204H
Description
The M67204H implements a first-in first-out algorithm, featuring asynchronous read/write operations. The FULL and EMPTY flags prevent data overflow and underflow. The expansion logic allows unlimited expansion in word size and depth with no timing penalties. Twin address pointers automatically generate internal read and write addresses, and no external address information is required for the Atmel FIFOs. address pointers are automatically incremented with the write pin and read pin. The 9 bits wide data are used in data communications applications where a parity bit for error checking is necessary. The retransmit pin reset the read pointer to zero without affecting the write pointer. This is very useful for retransmitting data when an error is detected in the system. Using an array of eight transistors (8T) memory cell, the M67204H combines an extremely low standby supply current (typ = 0.1 A) with a fast access time at 15 ns over the full temperature range. All versions offer battery backup data retention capability with a typical power consumption at less than 2 W. The M67204H is processed according to the methods of the latest revision of the MIL PRF 38535 (Q and V) or ESCC 9000.
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Block Diagram
Pin Configuration
DIL ceramic 28-pin 300 mils FP 28-pin 400 mils
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M67204H
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M67204H
Pin Description
Names FF XO/HF XI FL/RT VCC GND I0-8 Q0-8 W R RS EF Description Full Flag Expansion Out/Half-Full Flag Expansion IN First Load/Retransmit Power Supply Ground Inputs Outputs Write Enable Read Enable Reset Empty Flag
Data In (I0 - I8) Reset (RS)
Data inputs for 9-bit data Reset occurs whenever the Reset (RS) input is taken to a low state. Reset returns both internal read and write pointers to the first location. A reset is required after power-up before a write operation can be enabled. Both the Read Enable (R) and Write Enable (W) inputs must be in the high state during the period shown in Figure 1 (i.e. tRSS before the rising edge of RS) and should not change until tRSR after the rising edge of RS. The Half-Full Flag (HF) will be reset to high After Reset (RS). Figure 1. Reset
Notes:
1. EF, FF and HF may change status during reset, but flags will be valid at tRSC. 2. W and R = VIH around the rising edge of RS.
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Write Enable (W)
A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set. Data set-up and hold times must be maintained in the rise time of the leading edge of the Write Enable (W). Data is stored sequentially in the Ram array, regardless of any current read operation. Once half the memory is filled, and during the falling edge of the next write operation, the Half-Full Flag (HF) will be set to low and remain in this state until the difference between the write and read pointers is less than or equal to half of the total available memory in the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write operations. On completion of a valid read operation, the Full Flag (FF) will go high after TRFF, allowing a valid write to begin. When the FIFO stack is full, the internal write pointer is blocked from W, so that external changes to W will have no effect on the full FIFO stack.
Read Enable (R)
A read cycle is initiated on the falling edge of the Read Enable (R) provided that the Empty Flag (EF) is not set. The data is accessed on a first in/first out basis, not with standing any current write operations. After Read Enable (R) goes high, the Data Outputs (Q0 - Q8) will return to a high impedance state until the next Read operation. When all the data in the FIFO stack has been read, the Empty Flag (EF) will go low, allowing the "final" read cycle, but inhibiting further read operations whilst the data outputs remain in a high impedance state. Once a valid write operation has been completed, the Empty Flag (EF) will go high after tWEF and a valid read may then be initiated. When the FIFO stack is empty, the internal read pointer is blocked from R, so that external changes to R will have no effect on the empty FIFO stack. This is a dual-purpose input. In the Depth Expansion Mode, this pin is connected to ground to indicate that it is the first loaded (see Operating Modes). In the Single Device Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by connecting the Expansion In (XI) to ground. The M67204H can be made to retransmit data when the Retransmit Enable Control (RT) input is pulsed low. A retransmit operation will set the internal read point to the first location and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be in the high state during retransmit. The retransmit feature is intended for use when a number of writes equals to or less than the depth of the FIFO has occured since the last RS cycle. The retransmit feature is not compatible with the Depth Expansion Mode and will affect the Half-Full Flag (HF), in accordance with the relative locations of the read and write pointers.
First Load/Retransmit (FL/RT)
Expansion In (XI)
This input is a dual-purpose pin. Expansion In (XI) is connected to GND to indicate an operation in the single device mode. Expansion In (XI) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or Daisy Chain modes. The Full Flag (FF) will go low, inhibiting further write operations when the write pointer is one location less than the read pointer, indicating that the device is full. If the read pointer is not moved after Reset (RS), the Full Flag (FF) will go low after 4096 writes. The Empty Flag (EF) will go low, inhibiting further read operations when the read pointer is equal to the write pointer, indicating that the device is empty.
Full Flag (FF)
Empty Flag (EF)
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M67204H
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M67204H
Expansion Out/Half-full Flag (XO/HF)
This is a dual-purpose output. In the single device mode, when Expansion In (XI) is connected to ground, this output acts as an indication of a half-full memory. After half the memory is filled and on the falling edge of the next write operation, the Half-Full Flag (HF) will be set to low and will remain set until the difference between the write and read pointers is less than or equal to half of the total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse to the next device when the previous device reaches the last memory location.
Data Output (Q0 - Q8)
DATA output for 9-bit wide data. This data is in a high impedance condition whenever Read (R) is in a high state.
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Functional Description
Single Device Mode
A single M67204H may be used when the application requirements are for 4096 words or less. The M67204H is in a Single Device Configuration when the Expansion In (XI) control input is grounded (see Figure 2). In this mode the Half-Full Flag (HF), which is an active low output, is shared with Expansion Out (XO).
Figure 2. Block Diagram of Single 4096 bits x 9
(HALF-FULL FLAG) ) WRITE (W) HF 9 DATAIN (I) (Q) 9 DATAOUT (R) READ
FULL FLAG RESET
(FF) (RS)
(EF) EMPTY FLAG (RT) RETRANSMIT
EXPANSION IN (XI)
M67204H
Width Expansion Mode
Word width may be increased simply by connecting the corresponding input control signals of multiple devices. Status flags (EF, FF and HF) can be detected from any device. Figure 3 demonstrates an 18-bit word width by using two M67204H. Any word width can be attained by adding additional M67204H.
Figure 3. Block Diagram of 4096 bits x 18 FIFO Memory Used in Width Expansion Mode
Note:
Flag detection is accomplished by monitoring the FF, EF and the HF signals on either (any) device used in the width expansion configuration. Do not connect any output control signals together.
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M67204H
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M67204H
Table 1. Reset and Retransmit Single Device Configuration/Width Expansion Mode
Inputs Mode Reset Retransmit Read/Write Note: RS 0 1 1 RT X 0 1 XI 0 0 0 Internal Status Read Pointer Location Zero Location Zero Increment Write Pointer Location Zero Unchanged Increment(1) EF 0 X X Outputs FF 1 X X HF 1 X X
1. Pointer will increment if flag is high.
Table 2. Reset and First Load Truth Table Depth Expansion/Compound Expansion Mode
Inputs Mode Reset First Device Reset All Other Devices Read/Write Note: RS 0 0 1 RT 0 1 X XI
(1) (1) (1)
Internal Status Read Pointer Location Zero Location Zero X Write Pointer Location Zero Location Zero X EF 0 0 X
Outputs FF 1 1 X
1. XI is connected to XO of previous device. See Figure 4.
Depth Expansion (Daisy Chain) Mode
The M67204H can be easily adapted for applications which require more than 4096 words. Figure 4 demonstrates Depth Expansion using three M67204H. Any depth can be achieved by adding additional M67204H. The M67204H operates in the Depth Expansion configuration if the following conditions are met: 1. The first device must be designated by connecting the First Load (FL) control input to ground. 2. All other devices must have FL in the high state. 3. The Expansion Out (XO) pin of each device must be connected to the Expansion In (XI) pin of the next device. See Figure 4. 4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag (EF). This requires that all EF's and all FFs be ORed (i.e. all must be set to generate the correct composite FF or EF). See Figure 4. 5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth Expansion Mode.
Compound Expansion Module
It is quite simple to apply the two expansion techniques described above together to create large FIFO arrays (see Figure 5).
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Bidirectional Mode
Applications which require data buffering between two systems (each system being capable of Read and Write operations) can be created by coupling M67204H as shown in Figure 6. Care must be taken to ensure that the appropriate flag is monitored by each system (i.e. FF is monitored on the device on which W is in use; EF is monitored on the device on which R is in use). Both Depth Expansion and Width Expansion may be used in this mode. Two types of flow-through modes are permitted: a read flow-through and a write flowthrough mode. In the read flow-through mode (Figure 17) the FIFO stack allows a single word to be read after one word has been written to an empty FIFO stack. The data is enabled on the bus at (tWEF + tA) ns after the leading edge of W which is known as the first write edge and remains on the bus until the R line is raised from low to high, after which the bus will go into a three-state mode after tRHZ ns. The EF line will show a pulse indicating temporary reset and then will be set. In the interval in which R is low, more words may be written to the FIFO stack (the subsequent writes after the first write edge will reset the Empty Flag); however, the same word (written on the first write edge) presented to the output bus as the read pointer will not be incremented if R is low. On toggling R, the remaining words written to the FIFO will appear on the output bus in accordance with the read cycle timings. In the write flow-through mode (Figure 18), the FIFO stack allows a single word of data to be written immediately after a single word of data has been read from a full FIFO stack. The R line causes the FF to be reset, but the W line, being low, causes it to be set again in anticipation of a new data word. The new word is loaded into the FIFO stack on the leading edge of W. The W line must be toggled when FF is not set in order to write new data into the FIFO stack and to increment the write pointer. Figure 4. Block Diagram of 12288 bits x 9 FIFO Memory (Depth Expansion)
Data Flow - Through Modes
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M67204H
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M67204H
Figure 5. Compound FIFO Expansion
Notes:
1. For depth expansion block see section on Depth Expansion and Figure 4. 2. For Flag detection see section on Width Expansion and Figure 3.
Figure 6. Bidirectional FIFO Mode
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Electrical Characteristics
Absolute Maximum Ratings
Supply Voltage (VCC - GND):.............................- 0.5V to 7.0V *NOTICE:
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Input or Output Voltage Applied:. (GND - 0.3V) to (Vcc + 0.3V)
Storage Temperature: .................................. - 65 C to + 150 C
DC Parameters
Table 3. DC Test Conditions TA = - 55C to + 125C; Vss = 0V; Vcc = 4.5V to 5.5V
Parameter ICCOP (1) ICCSB (2) ICCPD (3) ILI (4) ILO (5) VIL
(6)
Description Operating supply current Standby supply current Power down current Input leakage current Output leakage current Input low voltage Input high voltage Output low voltage Output high voltage Input capacitance Output capacitance
M M67204H-30 110
M M67204H-15 120
Unit mA
Value Max
5
5
mA
Max
400 1 1 0.8 2.2 0.4 2.4 8 8
400
A A A V V V V pF pF
Max Max Max Max Min Max Min Max Max
VIH(6) VOL
(7)
VOH (7) C IN
(8)
C OUT (8) 1. 2. 3. 4. 5. 6. 7. 8.
Icc measurements are made with outputs open. R = W = RS = FL/RT = VIH. All input = Vcc. 0.4 Vin Vcc. R = VIH, 0.4 VOUT VCC. VIH max = Vcc + 0.3V. VIL min = -0.3V or -1V pulse width 50 ns. For XI input, VIH= 2.8V Vcc min, IOL = 8 mA, IOH = -2 mA. Guaranteed but not tested.
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M67204H
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M67204H
AC Parameters
AC Test Conditions Input pulse levels: Gnd to 3.0V Input rise/Fall times: 5 ns Input timing reference levels: 1.5V Output reference levels: 1.5V Output load: See Figure 7 Figure 7. Output Load
Table 4. AC Test Conditions
M67204H- 15 Symbol (1) Read Cycle TRLRL TRLQV TRHRL TRLRH TRLQX TWHQX TRHQX TRHQZ Write Cycle TWLWL TWLWH TWHWL TDVWH TWHDX Reset Cycle TRSLWL TRSLRSH TWHRSH tRSC tRS tRSS Reset cycle time Reset pulse width Reset set-up time
(5)
M67204H- 30 Min. Max. Unit
Symbol (2)
Parameter (3) (4)
Min.
Max.
tRC tA tRR tRPW tRLZ tWLZ tDV tRHZ
Read cycle time Access time Read recovery time Read pulse width (5) Read low to data low Z
(6)
25
15
40
30
ns ns ns ns ns ns ns ns
10 15 0 3 5 -
15
10 30 5 5 5 -
20
Write high to data low Z (6) (7) Data valid from read high Read high to data high Z (6)
tWC tWPW tWR tDS tDH
Write cycle time Write pulse width(5) Write recovery time Data set-up time Data hold time
25 15 10 9 0
-
40 30 10 18 0
-
ns ns ns ns ns
25 15 20
-
40 30 30
-
ns ns ns
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Table 4. AC Test Conditions (Continued)
M67204H- 15 Symbol (1) TRSHWL Retransmit Cycle TRTLWL TRTLRTH TWHRTH TRTHWL Flags TRSLEFL TRSLFFH TRLEFL TRHFFH TEFHRH TWHEFH TWLFFL TWLHFL TRHHFH TFFHWH Expansion TWLXOL TWHXOH TXILXIH TXIHXIL TXILRL 1. 2. 3. 4. 5. 6. 7. tXOL tXOH tXI tXIR tXIS Read/Write to XO low Read/Write to XO high XI pulse width XI recovery time XI set-up time - - 15 10 10 15 15 - - - - - 30 10 10 30 30 - - - ns ns ns ns ns tEFL tHFH, tFFH tREF tRFF tRPE tWEF tWFF tWHF tRHF tWPF Reset to EF low Reset to HF/FF high Read low to EF low Read high to FF high Read width after EF high Write high to EF high Write low to FF low Write low to HF low Read high to HF high Write width after FF high - - - - 15 - - - - 15 25 25 25 25 - 15 20 30 30 - - - - - 30 - - - - 30 30 30 30 30 - 30 30 30 30 - ns ns ns ns ns ns ns ns ns ns tRTC tRT tRTS tRTR Retransmit cycle time Retransmit pulse width(5) Retransmit set-up time(6) Retransmit recovery time 25 15 15 10 - - - - 40 30 30 10 - - - - ns ns ns ns Symbol (2) tRSR Parameter (3) (4) Reset recovery time Min. 10 Max. - M67204H- 30 Min. 10 Max. - Unit ns
STD symbol. ALT symbol. Timings referenced as in ac test conditions. All parameters tested only. Pulse widths less than minimum value are not allowed. Values guaranteed by design, not currently tested. Only applies to read data flow-through mode.
Figure 8. Asynchronous Write and Read Operation
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M67204H
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M67204H
Figure 9. Full Flag from Last Write to First Read
Figure 10. Empty Flag from Last Read to First Write
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Figure 11. Retransmit
Figure 12. Empty Flag Timing W
t
WEF
EF
t
RPE
R
Figure 13. Full Flag Timing
Figure 14. Half-Full Flag Timing
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M67204H
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M67204H
Figure 15. Expansion Out
Figure 16. Expansion In
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Figure 17. Read Data Flow - Through Mode
Figure 18. Write Data Flow - Through Mode
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M67204H
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M67204H
Ordering Information
Reference Number MMCP-67204HV-15-E(1) SMCP-67204HV-15SCC SMCP-67204HV-30SCC 5962-8956810QTC 5962-8956809QTC 5962-8956810VTC 5962-8956809VTC 5962D8956810VTC 5962D8956809VTC MMDP-67204HV-15-E SMDP-67204HV-15SCC SMDP-67204HV-30SCC 5962-8956810QNC 5962-8956809QNC 5962-8956810VNC 5962-8956809VNC 5962D8956810VNC 5962D8956809VNC MM0 -67204HV-15-E(1) MM0 -67204HV-15SV Note:
(1)
Temperature Range 25C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C 25C -55 to +1251C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C -55 to +125C 25C -55 to +125C
Speed 15 ns 15 ns 30 ns 15 ns 30 ns 15 ns 30 ns 15 ns 30 ns 15 ns 15 ns 30 ns 15 ns 30 ns 15 ns 30 ns 15 ns 30 ns 15 ns 15 ns
Package SB28.3 SB28.3 SB28.3 SB28.3 SB28.3 SB28.3 SB28.3 SB28.3 SB28.3 FP28.4 FP28.4 FP28.4 FP28.4 FP28.4 FP28.4 FP28.4 FP28.4 FP28.4 Die Die
Quality Flow Engineering Samples ESCC ESCC QML Q QML Q QML V QML V QML V RHA QML V RHA Engineering Samples ESCC ESCC QML Q QML Q QML V QML V QML V RHA QML V RHA Engineering Samples QML V
1. Contact Atmel for availability.
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Package Drawings
28-lead Side Braze 300 mils
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M67204H
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28-lead Flat Pack (400 mils)
19
M67204H
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Atmel Corporation
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4141J-AERO-04/07

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